Intern (Technical-Engineering)
Synopsys
Noida , INDIA
2d ago

and Requirements

  • The Verification Engineer is responsible for a wide variety of verification tasks, including designing self-checking test benches using modern verification techniques;
  • designing verification components such as bus functional models, monitors, and behavioral models.

    This position will also be responsible for analyzing and debugging simulation failures, as well as analyzing coverage results.

    Strong Verilog coding skills

    Strong debugging skills

    Strong C / C++ or Perl or python scripting skills

    Knowledge on FPGA Architectures

    Highly skilled with one or more industry standard simulation tools

    Strong understanding of typical design structures (FIFO’s, pipelines, memories, state machines, etc.)

    Excellent written and verbal communication skills

    B.Tech / M.Tech in EE from a reputed institute

    India

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