Analog Design Engr, Sr I
Hyderabad, INDIA
1d ago

and Requirements

As an analog design engineer in the PLL design team, the candidate would be responsible for system-level and circuit-level PLL design.

PLL designs will support high-speed Serdes designs such as PCI-Express, Ethernet, JESD and CPRI, as well as other applications.

The candidate will work with a team of designers based at Synopsys' site in Hyderabad and collaborate with other design teams in India and North America

Responsibilities and Duties

Custom circuit design in deep-submicron and FINFET CMOS technologies

Design of analog circuits such as VCOs, charge pumps and voltage regulators

Design of high-speed digital circuits such as dividers and clock distribution paths

Schematic entry and spice simulation of custom circuits

PLL top-level modeling and simulation

Qualifications and Experience

Post-graduate degree in analog CMOS circuit design, or equivalent experience

5 or more years of experience in CMOS analog circuit design

Detailed understanding of PLL loop operation and design

Design of PLL circuit components such as VCO's, charge-pumps, regulators and high-speed dividers

Design in deep-submicron and FINFET CMOS technologies

Hspice, Finesim or similar spice-type simulators

Schematic entry in Synopsys Custom Designer or similar tools

Knowledge of digital timing in PrimeTime and / or Nanotime is an asset


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