Power Modeling And Validation Engineer
Intel Corporation
Bangalore, KA, IN
6d ago

Job Description

IP level power & performance (PnP) modeling based on process, design, platform inputs using power modeling tool. This requires working with multiple stakeholders in various teams across IP / SoC and many geos

Support & ensure tech readiness phase with various what-if analysis on Architecture, process etc and come up with ideas for PnP improvement

Perform change analysis on regular cadence for various input parameters in the model and highlight the PnP impact

Pre to post silicon correlation, gap analysis and power debug

IPU (Imaging Processing Unit) PnP validation for all IPU versions and all related SOCs

Measure performance and power per IPU main block or function

Measure IPU power, performance and BW for the PI which are defined per SOC

Measure IPU logic power of main blocks : Leakage, idle power and active power

Check max PPC, efficiency, throughput and BW capabilities

Pre-requisites :

Good understanding of computer architecture w / clear concepts pertaining to transistor characteristics, leakage, Cdyn & P-V-T

Good understanding of MOS transistor and knowledge of dynamic and leakage power modeling. Basic knowledge on STA modeling and how to scale frequency across PVT corners

Exposure to Tcl scripting and basic data mining using IC Compiler and Prime Time PX will be beneficial

Working knowledge of hardware debug tools like LTB, JTAG, LA & O-scope

Working with SOC power method including Power Trace, SOCWatch, etc


Minimum 6 to 8 years of experience. B.Tech / M.Tech

Inside this Business Group

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