ASIC Design Engineer - New College Grad
India, Hyderabad
5h ago

What you'll be doing

Develop and enhance timing analysis / signoff work flow from frontend (pre-layout) to backend (post-layout) at both chip and block level.

Develop custom timing scripts using tcl / primetime for clock skew analysis, special circuits such as clock dividers, core logic

IO macros interfaces such as PCI-E, Frame-Buffer / Memory, HDMI, etc.

Chip level Integration, physically partitioning and floor planning.

Design optimization and timing convergence related tasks.

Development of PD work flows.

What we need to see :

BS or MS or equivalent experience in Electrical Engineering or Computer Science.

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