IP Enablement Manager Job Description In this position, the candidate will be responsible for the following .Pilot TFM methodologies on select IPG IPs to ensure smooth TFM transition for rest of IPG IPs as per planned cadence.
Improve TFM productivity and quality by evaluating new EDA tools and / or EC infrastructure. Develop design analytics to determine bottlenecks wherever necessary.
Work closely with PESG team to ensure that TFM methodology is robust for IPs before they are released to IP teams. Seeks feedback from IPG engineers to improve overall TFM productivity and qualityCoordinates TFM trainings across IPG Qualifications Qualification Master of Science (or a Master of Technology) degree in Electrical Engineering with more than ten years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than twelve years of relevant industry experience.
Experience Relevant ASIC design experience Expertise in verilog and system verilog based logic design Experience with IP Design Tool Flow methodologies Experience in Industry standard tools like Spyglass Lint, Spyglass CDC, DC, PT,LEC,VCS Experience in scan tools, VCLP, Calibre, Fishtail, Power artist Knowledge of scripting using perl / python / tcl / shell and unix commands Looking for highly motivated individuals who has passion to solve / debug TFM problems for IPs Ability to work with EDA vendors to solve Design tool issues.
Excellent leadership skills, presentation and people management skills Inside this Business Group The Infrastructure and Platform Solutions Group (IPSG) builds the silicon and platform infrastructure for Intel's silicon design teams.
IPSG is comprised of a reusable pool of infrastructure IP blocks, design enabling services such as tools and automation, and a best-in-class post silicon ecosystem that ramps quickly to high volume manufacturing and validation.
Our primary mission is to protect Intel's brand by providing the infrastructure necessary to enable all of Intel's products to hit the market on a dependable and predictable cadence.
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