Verification Engineer
Ethos HR
Ahmedabad
5d ago
  • Minimum 2 years of team lead experience.
  • Minimum 4 years of experience in development of SV based testbench.
  • Minimum 4 years of experience in development of SV based testbench.
  • Minimum 4 years of experience in verification of SoC or reasonably big size RTL design.
  • Project Planning Development, Verification and Validation Plan and Project Schedule participation. Architecture definition testbench architecture supporting multi language, multi tools and multi methodologies.
  • HDL Coding Verilog.
  • HVL Coding System Verilog.
  • Development : Testbench Coding, Test Scenario Coding / Definition, Assertion, protocol checkers and functional coverage coding.
  • Constrained Random Verification System Verilog.
  • Standards : Should have exposure to Ethernet, PCI, MIPI, USB, HBM specifications.
  • Configuration Management
  • Review and Audit participation
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