Sr. Validation Architect
Bangalore, KA, IN
2d ago

Job Description

We are looking for strong senior talent to join us to define next generator Validation Strategy and Architecture. As a Validation Architect, candidate will be responsible for defining strategy and quality for pre-silicon validation, should be working with the team for improvements required in the validation methodology, review and sign off of Validation Architecture Spec, Global Validation Plan, test plan, corrective & preventive action plans.

Validation Architect will be responsible for working with overall Validation team across different phase of programs starting from TR & Early enablement of validation environment, reviews, milestone & TI sign off.

As a technical leader on Validation, candidate will drive Innovation and changes required in Validation to incorporate ML / AI based strategic initiatives to improve quality and efficiency.

Candidate will be the focal point across organizational partnerships in Architecture, Design, System software developers and Validation teams within Intel across different sites.

The person should have broad understanding of multiple system areas (like memory controller, Power management, PCIe, USB / TCSS, Serial IO, Graphics, media, audio and other modules of varying complexity) and has excellent written and verbal communication to communicate the technical details with the validation engineers and project status, next steps, and needs with program leads and upper management.

Candidates must have the following :

  • Proven expertise in Silicon Product development and leading Design / Verification / Validation teams.
  • Extensive experience in creating verification environment from scratch for IP / Subsystem / SoC Pre si Verification.
  • Expertise in validating complex IPs from different sources.
  • In depth knowledge of system Verilog and verification methodologies like OVM, UVM is a must have.
  • Experience in leading pre si verification team on multiple projects, sound understanding of functional test strategies, directed, random, stress test generation, debug flows, scenario validation is a strong requirement.
  • Proven experience working as an individual and as part of high performing team to deliver product starting from creation of spec, verification infrastructure and execution strategy and delivering product is a strong requirement.
  • Experience in silicon bring up, debug in the lab.
  • Conversant with futuristic technologies on Validation including AI & ML based ones
  • Lead and be able to influence validation execution functions across multiple products.
  • Qualifications

    BS / MS / Ph.D degree in Electrical Engineering or related field of study with a minimum of 18+ years of relevant experience in SoC / IP / System verification / validation.

    Candidate should have proven track record of successfully validating end to end & delivering multiple products.

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