Company : Mentor Graphics
Job Title : Senior Applications Engineer - 10192
Job Location : India - Bangalore
Job Category : R&D / Software Engineering
Job Duties :
As part of a highly skilled team , help grow customer satisfaction with Mentor s DFT tools by helping them successfully deploy Automatic Test Pattern Generation (ATPG) and Built In Self -
Test (BIST) & Diagnosis tools (such as Fastscan , TestKompress , MemoryBIST , LogicBIST , BoundaryScan & Scan).
Work with customers with varying design styles and methodologies to architect the most effective technical solutions.
Should be able to provide expert advice and contribute to technical campaigns in other regions.
Identify and qualify potential new business opportunities and work the account teams to create an engagement plan.
Help the account team in growing the business by increasing adoption of Mentor DFT technology at customers.
Recognize and communicate potential business opportunities to assist growth of Mentor s business
Work collaboratively with customer support engineers , account and engineering teams to successfully deploy Mentor s products and services
Up to 25% travel would be required in this position.
Job Qualifications :
1. As a member of the technical team , you will contribute to our success by helping customers deploy Mentor s DFT tools efficiently.
This is a challenging position that will assist in growing the DFT business in India. You will work closely with customers as well as engineering and account teams worldwide.
2. Need excellent communication and problem solving skills , program management skills , hands - on and a self - starter , able to work independently but still build relationships with Managers and with customers.
3. Deep knowledge and experience with VLSI design , HDL Synthesis , VLSI Testing and design for testability.
4. Experience with design , simulation , verification of ASIC / VLSI circuits and systems , design verification and product test generation preferred.
In - depth understanding of Design for Test (DFT) structures is required. This includes scan based testing , Compression , Memory BIST , Logic BIST , and Boundary Scan (1149.
1). Expertise in scan data compression methodologies is required.
5. Preferred experience in specific areas : Operating Systems : UNIX , Linux , Solaris.
Languages : Verilog (Behavioral , RTL , gate level) , VHDL (Behavioral , RTL , gate level) , Tcl , Perl , C / C . Knowledge of spice , circuit simulations is an advantage.
CAD Tools : DFT Insertion , ATPG , Memory BIST , Logic BIST , Boundary Scan along with STA , Synthesis & Simulation exposure.
Familiarity with post silicon bring up and Diagnosis is a plus.
6. Minimum 5 years of design experience in DFT solution implementation , and a good understanding of backend design. Hands on experience in Memory BIST and / or Logic BIST implementation will be a big plus.
7. Education : Bachelors in Electrical / Electronics Engineering (min). Masters in Electrical Engineering is a plus,