Senior Physical Design Engineer
AQUANTIA CORP
Pune, Canada
4d ago

About Marvell At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology.

Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions.

Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform for the better.

The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing.

If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below. The Opportunity About Marvell Marvell is empowering the global data economy.

Whether at the network core or edge, our leading technologies make it possible for the world’s data to be processed, moved, stored and secured faster and more reliably.

With leading intellectual property and deep system-level knowledge, Marvell's infrastructure semiconductor solutions are transforming the 5G, cloud computing, enterprise and automotive markets of tomorrow.

At Marvell, you’ll see your ideas put to work, share in the success of our company, and achieve a healthy life-work balance in a strong culture of corporate citizenship and global semiconductor leadership.

If you are ready to excel, innovate, and truly enjoy where you work, apply now for the position detailed below. Roles and Responsibilities The roles and responsibilities of engineer require in-depth knowledge and hands-on experience across the entire spectrum of RTL2GDSII Implementation i.

e. Synthesis, Floorplanning, Power Grid Design, Placement, Clock implementation, Routing, STA, Electrical signoff, Power-Analysis, Physical Verification, Chip finishing, etc.

Interact with FE / BE design teams to prepare good floorplan and suggest appropriate changes to achieve PPA goal Interact with the design team to understand timing, CTS goals in detail to solve problems and propose physical design ideas Debug design, timing constraint issues and feedback to design team Analyze results from signoff checks and achieve design closure Required Skills 5 to 14 years of experience in Physical Design implementation and physical verification role Must have led and been primarily responsible for at least 2 end-to-end multi-million gate-count hierarchical full-chip Physical design projects Ability to plan and work independently and coordinate with cross-functional teams Must have led and been primarily responsible for at least 2 end-to-end multi-million gate-count hierarchical full-chip Physical design projects Ability to plan and work independently and coordinate with cross-functional teams Good knowledge of low power concepts and application to PD Low power synthesis on blocks and subsystems using DC / Genus, Physical Aware synthesis Experience in design planning and Integration activity IO, Bump planning and RDL routing Strategy Experience in formal verification for RTL 2 gates and gates2gates, low power verification is a must Exposure to low-power designs with CPF / UPF flow Knowledge of CTS, Clock tree methodology and clock skewing Power grid, clock tree, and low-power reduction implementation methods Good understanding of timing constraints development excellent STA tool and timing concept understanding for analysis & debug of problems and closure methodologies Signal integrity and timing closure issues such as OCV / AOCV / Statistical Timing / MMMC and multi-power designs (Level shifters, Isolation cells etc.

Must have experience in ECO implementation Understanding of Physical Verification Flows is an advantage Programming and scripting skills (Tcl, Perl, etc.

Experience with cutting edge technology node designs like 16nm, 12nm, 7nm Experience of networking design would be a plus Hands-on expertise with industry-standard EDA tools including but not limited to Design Compiler / RTL Compiler, Innovus / ICC2, Primetime / Tempus, QRC / StarXT, Calibre The Perks With competitive compensation and great benefits, you will enjoy our workstyle within an incredible culture.

We’ll give you all the tools you need to succeed so you can grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

Your Future Marvell provides a work environment that promotes employee growth and development. We are searching for an individual who wants to grow with the company and will strive to improve performance.

If you are driven, personable, and energetic, there will be additional opportunities for you here at Marvell. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Regards, Anurag The Perks With competitive compensation and great benefits, you will enjoy our workstyle within an incredible culture.

We’ll give you all the tools you need to succeed so you can grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

Your Future Marvell provides a work environment that promotes employee growth and development. We are searching for an individual who wants to grow with the company and will strive to improve performance.

If you are driven, personable, and energetic, there will be additional opportunities for you here at Marvell. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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