Senior SOC Design Engineer
Intel Corporation
Bangalore, KA, IN
1d ago

Job Description

The Extreme throughput Computing Processor and Accelerator(ECPA) group within the Scalable Data Center Silicon Group(SDSG) organization is responsible for the development of Servers and Accelerator(AI) for Data-center / cloud applications.

Main Duties and Responsibilities :

We're looking for Passionate, enthusiastic, motivated and self-driven engineer with expertise in area of Full Chip Floor planning(FCFP), who will bring a lot of changes & innovations in cutting-

edge technologies by their talent to collaborate with cross site teams and be a part of their Engineering excellence by taking care of following responsibilities :

Expected to take independent ownership of complex multi-million Server / AI SOC w.r.t Full chip Floor-planning, IO planning, Power planning, ESD, Place & Route and CTS using physical design tools.

Expected to drive and influence discussions with various stakeholders, including IPs, Architecture, Front-end and packaging for optimal and faster Floorplan convergence

Own Physical Integration of sub chips and subsystems.

Physical Design Methodology


BS in Electrical or Computer Engineering with 12+ years' experience or MS in Electrical or Computer Engineering with 10+ years' experience in handling end2end execution of complex SoC with focus on Full chip floor-

planning as primary responsibility.

Excellent verbal and written communication skills.

Preferably experience in 7 nm, 10 nm & 14nm flows

Performing a wide range of back-end activities, including synthesis of RTL, DFT insertion, power optimization Floor-planning, PnR (Place and Route), Clock Tree Synthesis (CTS), Timing closure (STA), DRC, LVS, Antenna checks, IR drop (RedHawk), multi voltage checks etc.

Participating in the development of a back-end ASIC design flow.

Expertise in Synopsys suite (IC Compiler, Primetime, Design Compiler).

Experience of UPF low power design through synthesis, place and route.

Inside this Business Group

Legal Disclaimer :

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