What you do at AMD changes everything
At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies building blocks for gaming, immersive platforms, and the data center.
Developing great technology takes more than talent : it takes amazing people who understand collaboration, respect, and who will go the extra mile to achieve unthinkable results.
It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.
If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
Be a critical member of the team that plays a significant role in ensuring the quality of next generation Zen Microprocessors.
Develop and execute pre-silicon verification test plans for DFT features of the next gen Zen architecture based Cores and SoCs.
Develop directed and random verification tests to fully validate the DFT functionality.
Verify DFT design blocks and subsystems (such as JTAG, MBIST, high speed IO PHY, Scan, Security, Fuse, Clocks, Resets, etc) using complex SV or C++ verification environments.
Construct SystemVerilog and / or C / C++ models and test sequence libraries for simulation.
Build test bench components including Agents, Monitors and Scoreboards for DUT. Compose tests, assertions, checkers, validation vectors and coverage bins to ensure verification completeness.
Debug regression test failures to expose specification and implementation issues. Identify and address areas of concern to meet design quality objectives.
Develop high coverage and cost effective test patterns, and take part in ATE bring-up.
Post silicon ATE and System level debug support of the test patterns delivered. Optimize the test patterns to improve the test quality and reduce test costs.
Required Qualifications :
Minimum 5 years of experience in DFT feature verification (such as JTAG, MBIST, SCAN, fuse, IO-PHY loopback testing)
Strong background in Verilog, SystemVerilog (SV), SVA, UVM verification methodologies and C++
Strong debug skills and experience with debug tools such as Verdi.
Experience with EDA simulation tools like Synopsys VCS, Cadence NCSIM, Verdi
Experience with scripting languages like Tcl / Perl / Ruby / Python
Working knowledge of Unix / Linux OS, file version control.
Additional skills :
Experience in ATE debug, Synthesis, formal / LEC, or power analysis will be a plus.
Strong analytical / problem solving skills and pronounced attention to details
Knowledge of STA Constraints for various DFT modes.
Excellent written and verbal communication
Engineering Degree in Electronics / Electrical / Computer Science with 3-5 years of industry experience