Lead engineer
HARMAN INTERNATIONAL
Bengaluru / Bangalore, INDIA
4d ago
source : TimesJobs

What You Will Do 1. Atleast 3 years of experience in Verilog & System Verilog. Should be proficient in UVM. 2. Experience with UVM / BFM generation, writing System Verilog scoreboards & checkers.

3. Should have experience using ASIC design tools such as VCS, Verdi, NCVerilog. Knowledge of scripting languages (Shell, Perl, Python), C language is a plus.

4. Prior experience in Machine learning / Artificial Intelligence domain is a plus. Additional Job Description 5. Prior experience in Machine learning / Artificial Intelligence domain is a plus.

6. Setting up Gate Level Simulations environment from scratch. 7. Experience with FPGA Verification What You Need 1. Atleast 3 years of experience in Verilog & System Verilog.

Should be proficient in UVM. 2. Experience with UVM / BFM generation, writing System Verilog scoreboards & checkers. 3. Should have experience using ASIC design tools such as VCS, Verdi, NCVerilog.

Knowledge of scripting languages (Shell, Perl, Python), C language is a plus. 4. Prior experience in Machine learning / Artificial Intelligence domain is a plus.

Additional Job Description 5. Prior experience in Machine learning / Artificial Intelligence domain is a plus. 6. Setting up Gate Level Simulations environment from scratch.

7. Experience with FPGA Verification

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