Hands on design experience in clocking and high speed serial interface IP design in cutting edge technology nodes.
Must have 14+ years of experience in analog design and at least a few years in leading / mentoring teams.
Desired experience in leading multiple rounds of complex analog IP design- right from spec, circuit architecture to post silicon debug.
Must have excellent communication skills and should be team player.
Desired skills include working knowledge of behavioural modelling of analog blocks and AMS simulations
Flair in driving execution and project tracking is desired
Lead Circuit Design for high speed serial interface PHY (PCIe gen4 / 5 USB4, development. Role entails driving this all the way from circuit architecture, execution to post silicon debug activities.
He / she will oversee design reviews, layout implementation, behavioural modelling, AMS simulations etc towards a high quality IP delivery.
Will provide technical insights and review to other circuit designers..
BS / MS - EE / CS and 14+ Years of industry experience.