In a fast paced leading edge environment with endless possibilities of innovating and learning, you will be responsible for ensuring EM / IR reliability of complex IP's such as GFX, Imaging processors, peripheral subsystems like PCIe, TypeC , Display, Media etc and other high speed design like Memory subsystems / DDR , High Speed Serial IO's etc.
Key responsibilities include but not limited to - Power Delivery network planning and implementation to meet EM / IR reliability verification criteria for IP blocks, implementation of necessary fixes to meet set criteria and liaison with Physical Design Engineer and Design Automation Engineer to drive sign-
off of IP's. The responsibility may also include ESD protection compliance verification of complex IP's. Extraction of Power networks or full IP design to perform selected path analysis.
Propose methodology gaps and drive changes to improve efficiency and turn-around time.
Mtech / Btech in field of computer engineering / science with 3+ or 5+ years of experience respectively. Experience in Industry standard RV EM / IR analysis tools.
Viz., Redhawk, Redhawk-Seascape, Power artist, Totem. Experience in designing power rails to meet EM / IR requirements, IP or SoC level Power delivery network design experience would be a requirement.
Experience in basic automation skills in Tcl and Perl would be a requirement. Understanding of SoC / IP level floor-planning would be an advantage.
Knowledge of ICC or Industry standard APR tools would be an added advantage. Experience in any one of the industry standard backend extraction tools would be a desirable qualification.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms.
PEG strives to lead the industry moving forward through product innovation and world class engineering.
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