Creates bottomsup elements of chip design including but not limited to FET, cell, and blocklevel custom layouts, FUBlevel floor plans, abstract view generation, RC extraction and schematictolayout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation, customer polygon editing, autoplace and route algorithms, floor planning, fullchip assembly, packaging, and verification.
Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and / or flow developments.
Requires expansive knowledge and practical application of methodologies and physical design.
Experienced Physical Design Team Manager - Bangalore
Inside this Business Group
Legal Disclaimer :
Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews.
We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money.
We would urge people interested in working for Intel, to apply directly at and not fall prey to unscrupulous elements.