Design Verification Engineer
Synopsys Inc
Hyderabad, Telangana, India
3d ago
source : Linkedin

Verification Applications Engineer.

The candidate will be a member of the Customer Success Group which offers the industry leading RTL verification platform.

VCS provides advanced, built-in technologies, including full-featured testbench, complete assertion support, a library of assertion checkers and comprehensive coverage and analysis, to enable smart verification of complex system-on-chip designs.

The Verification IP (VIP) libraries offer a complete line of behavioral models, checkers and suite of compliance tests for advanced on-chip protocols.

The Formal Verification Tools offer static and formal methods that are the best in class. The Hardware Assisted Verification and Emulation Systems shorten the time to silicon by delivering exceptional performance and debug features.

Application Engineer (AE) position gives you the opportunity to be a part of a fantastic team working on Synopsys Verification Platform, primarily on VCS simulator used by every major hardware company in the world.

The responsibilities involve providing pre / post-sales technical support, analysis of customers current verification methodology, presentation and deployment of verification methodologies, driving verification benchmarks, developing and delivering technical trainings, managing alpha and beta customer rollout.

As an AE, you will be responsible to interact and support key customers, help them analyze and resolve complex verification issues for their cutting edge ASIC designs, and learn to mold their technical requirements into a mutually rewarding growth opportunity.

Leveraging your close interaction with customers, R&D, Marketing, and Sales teams you will be able to influence development of next generation verification tools by defining the future direction and scope of enhancements, flows, and methodologies.

A successful candidate will be expected to have expertise in ASIC design / verification methodologies and technologies, passion to work with customers in achieving their verification goals, resolve issues in creative ways, exercise independent judgment in selecting methods and techniques to obtain solutions, ability to execute projects from start to completion, determine and develop recommendations to solutions and work on team-driven or task-oriented projects.

May guide more junior peers with aspects of their job. Networks with senior internal and external personnel in own area of expertise.

Desired Skills & Experience

Knowledge of VLSI design flow and methodology, Expertise in HDL / HVL including SystemVerilog, Verilog, VHDL, SystemC

Experience in front-end verification including RTL / TB coding, simulation debug

Proficient in UNIX usage, shell / Perl scripting

Strong communication skills, both verbal and written. Ability to lead and coordinate discussions in a small group as well as present them in an organized fashion to larger groups

Working experience on UVM Methodologies

Knowledge of Low Power Design / Verification, Debug using Verdi would be a plus

Typically requires a minimum of 5 years of related experience.

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence.

The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security.

If you share our passion for innovation, we want to meet you.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

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