Pre-Si Validation Engineer with the following responsibilities :
Leading Performance Validation focusing latency and bandwidth charaterization, performance modeling and competitive analysis.
Leading major cluster / top level verification, developing test environment, verification specification documentation and working with cross-
functional engineering teams on architecture, design and verification.
Working closely with Validation Architect in defining validation strategy and reviewing test plan.
Developing test plans and test environments; Developing tests in assembly, C, or SV according to test plans; Developing coverage monitors and analyze coverage to ensure all the test cases in the plans are covered.
Experience in OVM / UVM environment, developing testplans / testbenches, C-based transactors, and writing / debugging assembly based tests.
Experience with advanced verification techniques such as formal and assertions a plus.
Experience using an interpretive language such as Perl, Python or Ruby.
Experience in C or C++ programming a plus.
Experience in Post-Si bring-up a plus.
Strong analytical and debugging skills, and creative in problem solving.
Bachelors or Masters degree in Electrical, Electronics or Computer Engineering with 7+ years of Pre-Si Validation experience.
In-depth knowledge of digital logic design, chip architecture and microarchitecture.
Inside this Business Group
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