Working on various aspects of the digital ASICs; this includes architecture, design specification, micro architecture, RTL Coding (Verilog, SystemVerilog) for high speed, multiple clock domain networking ASIC, SoC design, Lint and CDC, specifying design constraints, Synthesis, Equivalence checking.
Responsible for design of an IP / subsystem (in HDL) starting from specifications, developing synthesizable micro-architecture with optimum area, power and timings.
The candidate is required to work on ARMv7-A processor based CPU system and is expected to be familiar with ARM CPU architecture and CPU system peripherals.
Provide support to IP verification, SoC verification and may get involved in block level or full chip test bench design and development, test plan development, test suite development and debug, PERL / TCL Scripting.
Review test plans from verification team and provide feedback.
Provide necessary support and work closely with the other teams like physical design, validation, SW / driver development.
Required Qualifications :
Bachelors / Masters Degree in Engineering with specialization in Electronics / VLSI from one of the reputed institutes
5 years of post qualification experience.
General requisites :