Lead Engineer - IP Design
NXP Semiconductors enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better and safer.
As the world leader in secure connectivity solutions for embedded applications, we are driving innovation in the secure connected vehicle, end-
to-end security & privacy and smart connected solutions markets.
Your main duties will be :
Evaluate, build and deploy the most efficient designs techniques for delivering increasingly complex SoC / IP digital designs and architecture within aggressive, market-driven schedules.
Own complete Front end design of an IP / SoC taking it from Concept through to silicon level 100% Spec Compliant mature design including Design / Verification and Pre-Si Validation cycle.
Ensure quality adherence during all stages of the project life cycle. Also carry out a thorough analysis of existing processes, recommend and implement the process improvements to ensure Zero Defect’ designs.
Encouraging and influencing technological innovations in the team
Ensure that SMART metrics are established and implemented, to measure the Design processes efficiency and achievement of goals.
Ability to work well as part of a team both locally, and also with remote or multi-site teams.
Key Skills :
Self starter with 5-7 years of experience on IP / SOC / Chip level / Sub-systems with multimillion Gate and complex Design including multiple clocks and power domains.
Should be able to work on these with minimal supervision.
Experience in microcontroller architecture, Cache, protocols like AHB / AMBA,AXI, Memory(Flash, SRAM,DDR) and memory controllers
Experience in automotive protocols like LIN, CAN, Flexray.
Graphics / Multimedia / Networking protocols like Ethernet, USB, ITU 656 would be an advantage.
Experience and extensive hands on knowledge of HDLs (Verilog / VHDL), Scripting languages (Perl, Tcl), C / C++ for hardware modeling.
Exposure to the various Front end Integration techniques using IPXACT, CSV Scripts.
Hands on work on pre silicon validation using FPGA / Palladium would be a significant added advantage.
Experience in Low power designs with various Clock gating, DVFS techniques.
Work on Testbench and Testplan development along with the verification team. Addressing of the Analog / Mixed signal and Testability aspects of the IP / SoC along with functional requirements would be an advantage.
B.Tech / M.Tech (ECE / Electrical)