Data Path Design Job Description In this position, you will be responsible for leading implementation of data path / custom design of sub-systems, formal equivalence checks, timing analysis and convergence of large sub-systems.
You will be part of C2DGgroup, in the Big Core design team driving Intel's latest CPU's in the latest process technology.
Your responsibilities will include but not limited to 1. Responsible for timing execution and convergence including setup and hold for greater than 5Ghz Freq and low-power digital designs.
2. Deep understanding of Static timing analysis concepts 3. Timing Convergence across all HVM targets 4. Close work with Layout & Floor planning teams 5.
Back end design implementation of new features 6. Post silicon performance push activities. Qualifications You must possess a Masters Degree in Electrical or Computer Engineering with at least 8 or more years of experience in related field or a Bachelors Degree with at least 10 years of experience.
Technical Expertise in synthesis, P&R tools and static timing analysis are required. Preferred Qualifications - Digital Design Experience in High Speed & Low Power design implementation - Minimum 8 years of experience in transistor level operation, memory bitcell design, design challenges under process variations and low power circuit techniques - Familiarity with Verilog / VHDL - Programming skills in TCL, Perl, Python and shell scripting.
2 years is an added advantage Inside this Business Group The Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intels leadership products.
This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences. IN JR0142339 Bangalore