experience with MCU and APU class processors.
experience with AXI / AHB or other standard on-chip buses.
Good knowledge of processor based SoC architecture.
Excellent debugging skills.
Broad understanding of RTL-to-Tapeout methodology.
Prior experience with pre and post silicon debug.
Implement logic / structural physical designs, such as RTL design, synthesis, floor planning, power-grid and clock tree designs, timing budgeting and closure, place and route, RC-extraction and integration.
Verify logic / structural physical designs, such as functional equivalency, timing / performance, noise, layout design rules, reliability and power.
Oversees definition, design, verification, and documentation for SoC System on a Chip development.
Determines architecture design, logic design, and system simulation.
Defines module interfaces / formats for simulationKEY WORDS.
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