The employee is responsible for complete physical design of multiple large & complex blocks & sub-system implementation 28nm / 16nm and below technology nodes.
The employee is expected to take ownership of Full Chip / multiple complex design & flow challenges, which would include Floor-planning, Place & Route and CTS using physical design tools Physical verification and IP Integration Physical Design Flow and Methodology Ability to lead the team along with the project execution Use metric-driven techniques to help ensure first-pass working silicon.
Communicate regularly with the implementation and project team to resolve issues, and communicate status to leads Occasional travel needed Job Requirements This position requires at least B.
E / B.Tech / M.Tech in Electronics with ASIC development experience in a fast paced environment with following experience.
Expertise in Physical Design activities Floor-planning, CTS, P&R, Extraction, Power IR / EM, Physical Verification (DRC / LVS) and Signal Integrity Static Timing / Crosstalk Analysis and timing closure Must have an understanding of Synthesis / DFT concepts and flow Experience in working with analog IP, hard and soft macros and delivering hierarchical design projects Expertise with Backend Tools (Innovus or ICC, PVS, Tempus, Voltus, QRC) Strong programming knowledge in Perl, TCL, and / or Shell and Python Scripting Excellent oral and written communications skills in order to work with teams across the globe