Req. ID : 184823
Our vision is to transform how the world uses information to enrich life.
Join an inclusive team focused on one thing : using their expertise in the relentless pursuit of innovation for customers and partners.
The solution we create help make everything from virtual reality experiences to breakthroughs in neural networks possible.
We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can spark the very innovation we are pursuing!
Position Description :
To be part of a highly skilled and challenging high speed PHY design team working on the latest technology nodes (12nm and below).
Take ownership of analog sub-blocks inside the PHY and drive the specification and implementation. It includes transistor and block level design, simulation, reliability and mixed mode simulations etc.
Drive layout of complex blocks through mask designers. Conform to complex process rules as well as DFM.
Participate in design reviews both internally and potentially with customers to explain design choices and robustness.
Work with people across multiple sites including overseas.
Help with creating IP EDA views : Behavioral / Verilog-A, timing views, abstract etc.
Participate in silicon bring up, characterization, & perform correlations against models & simulations.
Mentor and supervise junior engineers.
Equal opportunity position with excellent pay package!
SKILLS required :
Circuit design experience in analog / mixed signal CMOS circuits in deep sub-micron technologies (5 40 nm) in High speed Memory interfaces (DDR3 / 4 / 5, LPDDR3 / 4x / 5, GDDR5 / 6) or SerDes Interfaces (PCIe, MIPI, HDMI, USB, SATA etc).
Prior experience in taking full ownership of at least on of the sub-blocks like PLL, DLL, CDR, high speed receiver with equalization, transmitter front end and high speed data path.
High speed I / O cell designs such as DDR, LVDS, HSTL, CML.
Power Delivery circuits such as Bandgap, LDO, Bias circuits.
Strong fundamental knowledge for AMS design, Advanced CMOS and FinFet technologies.
Understanding of Mismatch analysis & Monte-Carlo methodology / sims, transistor level Circuit level noise analysis. Understanding of device physics & deep-sub micron issues.
Supervision of complex and / or sensitive analog layout and defining IP floorplan
Experience with industry standard tools such as Cadence ADE, Spectre, AMS verification, EM / IR flows, MATLAB, Calibre etc.
Working knowledge of Mixed mode simulation, Signal Integrity and ESD desired.
M.S. / M.Tech, BS / BE (Electronics)
Experience Required : 4-10 Years
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.
For US Sites Only : To request assistance with the application process and / or for reasonable accommodations, please contact Micron’s Human Resources Department at 1-800-336-8918 or 208-368-4748 and / or by completing our General Contact Form
Keywords : Bangalore Karnātaka (IN-KA) India (IN) NVE (Non-Volatile Engineering Group) Experienced Regular Engineering #LI-SK1 Tier 4