NXP Semiconductors enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better and safer.
As the world leader in secure connectivity solutions for embedded applications, we are driving innovation in the secure connected vehicle, end-
to-end security & privacy and smart connected solutions markets.
Specific skills & knowledge
Bachelor or Master or Ph.D. in Electronics Engineering and specialization in VLSI domain.Hands on experience in SoC level floor plan, power plan, IO ring, STA, Power integrity analysis and physical verification and defining analog / digital interface requirementsProven experience in delivering full chip Static Timing Analysis (STA) closure methodology of mixed signal SoC with high speed PHYs, IOs, PMU IP etc.
closing analog / digital interfaces timing & signal integrity issuesExperience in Synopsys Prime Time tool flow, Cadence Tempus tools, low geometry node issues, working with EDA team in reviewing & resolving blocking issues in projectExperience in customizing flows & methodology to meet low power & area objectives of SoC and leading team to execute on timeAbility to use scripting languages / automation of STA analysis methodology creation and deploymentShould have proven experience in demonstrating strong technical leadership to deliver on commitment, anticipation of challenges, assertive communication and excellent team player.
Excellent communication skills with proven experience in international relationships