Job Area Engineering - HardwareLocation India - BangaloreJob Overview The responsibility includes : - Independent planning and execution of Netlist-
to-GDSII. Full exposure to all aspects of design flows like floorplanning, placement, CTS, routing, crosstalk avoidance, physical verification Well versed with the level timing closure (STA), timing closure methodologies, ECO generation and predictable convergence.
Drive methodology with help of local and external CAD / EDA teams for faster design convergence Well aware of place and route methodologies and hands on experience with timing convergenceQualifications : -
Minimum Qualifications 4-15 yrs experience in Physical Design Execution- Should have good exposure to high frequency design convergence and descent exposure to physical design methodology-
Masters / Bachelors Degree in Electrical / Electronics science engineering with at least 4+ years of experience in IC design Experience in leading block level or chip level Timing closure & Physical Design activities.
micron design problems and solutions (leakage power, signal integrity, DFM etc.)- Tcl / Perl scripting Willing to handle technical deliveries with a small team of engineers.