Synthesis and Timing closure on 7nm / 5nm / Future sub-micron technologies at Hard Macro / Subsystem / SoC level.
Work on 7nm / 5nm / Future sub-micron Technologies
Co-work with RTL and DFT engineers, prepare SoC Top / Block level constraints
Synthesis of the Block and Top level RTL
Develop Floor-planning and CTS guidelines for layout. Working experience with Physical Design will be an added advantage.
Verify timing constraints with CCD
Analyze pre-layout and post-layout timing, generate Timing and Power ECOs, work closely with layout engineers to achieve full chip timing closure
Perform in-house quality check before P&R and after P&R.
Power domain checks for Block and Top, CLP
Requirement · Requirement
4 to 8 years working experience with top / block level Synthesis, Timing closure (STA), Physical Design
Good experience using PrimeTime and CCD
Good understanding of Deep Sub Micron topics
Well versed with TCL / Perl script
Experience handling UPF and Conformal Low Power checks
Ability to communicate effectively with multiple global cross-functional teams
Enthusiastic and ability to be an independent player and also work in teams
SoC level experience is a plus.