Responsibilities :
Ownership of complete physical implementation at block and chip level. Responsible for delivering timing clean blocks that meet design targets including DRC, LVS & IR closure.
Good understanding of chip level tasks like IO-ring, RDL routing. Familiarity across both wirebond and flipchip packages.
Work closely with the frontend design team to resolve design issues. Responsible for various flow setups like PNR, STA, IR & PV with expertise in scripting both for tool specific and automation (PERL and / or Python).
Requirements :
Our Silicon IP business is all about integrating more capabilities into an SoC faster. We offer the world’s broadest portfolio of silicon IP predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors.
All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications.
And get differentiated products to market quickly with reduced risk.
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence.
The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security.
If you share our passion for innovation, we want to meet you.
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Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
