Rtl Asic Design Engineer
S A Tech Software India Private Limited
17d ago

RTL Design Minimum of experience in RTL Logic design. RTL Integration experience at Subsystems SoC Candidate should have Worked on RTL Lint Lintra or Spyglass Lint design flows Required Experience on CDC analysis.

Required Experience on Febe flow Design Compiler fev For Logic handoff to Backend team Should have Worked on UPF Spyglass LP design flows Areas of interest are expertize in any one of them Domain a RTL design for digital signal processing logic design in Verilog like filter fft matrix

Add to favorites
Remove from favorites
My Email
By clicking on "Continue", I give neuvoo consent to process my data and to send me email alerts, as detailed in neuvoo's Privacy Policy . I may withdraw my consent or unsubscribe at any time.
Application form