Responsibilities : Complete understanding of the full chip power architecture for NCS design, works with the SD team on power architecture definition-
Own the full chip UPF for SoCs and carry out chip level lower power verification activities- Chip level power estimation and optimization-
Chip level RV analysis including Dynamic IR and thermal analysis- Work with TFM team on the methodology improvements and BKMs-
Work with partition owners for RV / LP verification reviews and debug- Interact with package / bonding team for power bump assignments and power routing improvements-
Full chip CPM generation and PDN analysis- Work with ESD team on clamp placement and ESD analysis
Qualifications : BE / BTech in EC / EE with 7+ years, MTech. in EC / EE with 6+ years Experience : Hands on experience of full chip low power verification, power estimation, power optimization and RV IR Drop / EM analysis-
Thorough understanding of UPF / CPF, lower power structures- Should be conversant with power reduction techniques- Should have sound knowledge of Redhawk / PTPX / Spyglass LP / Conformal LP / Formality-
Should be able to run SPICE simulations in HSPICE- Should be able to write scripts in TCL / Perl- Exposure to Intel flows would be additional advantage
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms.
PEG strives to lead the industry moving forward through product innovation and world class engineering.
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