Should be strong in technical concepts, fundamentals, and good team player. The role involves daily technical interaction with local, US counter parts.
He / She will be part of SNPS DDR / HBM IP implementation team and responsible for the implementation and integration of world class DDR IPs at the cutting-edge technology nodes (14nm,10nm and below).
Timing closure above 2GHz, mixed signal had macro IP integration, Building the efficient clock trees with very tight skew balancing are some of the challenges as part of day-to-day job.
Prior working knowledge in the DDR / HBM timing closure, implementation would be an added advantage.
This role is for a technical ladder and so it requires hands-on working knowledge preferably with SNPS tools like DC, PT, PT-SI and ICC2.
Typically requires 2-4 years of experience after graduation from a reputed university.
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