Job Description and Requirements
Job Description :
We are looking for a strong junior technical manager to help lead a group of mixed-signal engineers to undertake existing and some next generation DDR IP development.
The candidate should have expertise in source-synchronous systems, considerable practical experience with several designs under his / her belt who has interests in high-
speed, DDR memory interface design at the IC level. This position will be responsible for Engineering Document creation and maintenance, design reviews and general contributions to the development of existing and next-
generation physical layer interfaces for DDR PHY. To be successful in this position, you can develop and maintain schedules and work in cross-
functional settings while being proficient in design & verification. We will rely on your ability to multi-task in client support requests from time to time.
You should also be familiar with analog mixed-signal simulation strategies and having a good knowledge of Signal Integrity and / or Power Integrity is a plus.
you must possess a full understanding of high-speed analog / digital design areas (ie. Could be, but not limited to, transceivers, DDR, etc) and have working knowledge of multiple related areas that include DDR, SerDes and / or communication interfaces.
perform in project leadership role, and; contributes to complex aspects of a project. Furthermore, you will need to be independent and will occasionally receive general instructions on new assignments and projects.
representing the organization on business unit and / or company-wide projects; guiding more junior peers with aspects of their job and frequently networking with senior internal and external personnel in own area of expertise.
As a technical manager, you have leadership qualities, have lead developments, and you must have a strong desire to learn and explore new technologies while demonstrating good analysis and problem solving skills.
specifically, HSPICE, Matlab / Simulink as well as a standard knowledge in exercising mixed-signal verification flow (DRC, LVS, etc).