At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We looking for Analog Design engineers with experience in SerDes PHY design. The SerDes protocols of interest are : USB2, DPHY, MPHY, PCIe, USB3.
I am looking for people who can lead either IP level analog design or sub block level analog design so look for individual contributors between 2 to 15 yrs of exp
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