ASIC Digital Design Engr, Sr I
Synopsys, Inc
INDIA - Bangalore
6d ago

Job Description and Requirements

Job role :

The candidate will be part of the Solutions Group at our Bangalore Design Center, India. The position offers learning and growth opportunities.

This is a Senior Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in the Verification domain.

Job Responsibilities

  • Understand Standard Specifications / the functional specifications / feature enhancements for the product and create micro-
  • architecture and detailed design documents for some of the components of the Test Environment for the DesignWare family of synthesizable cores in protocol areas such as DDR / AMBA (AMBA2, AXI) / MIPI / Others

  • Be an individual contributor in the Verification Tasks coding of TE, debug, verification coverage improvement, etc.
  • Hands on SV UVM expertise.
  • Will contribute to technical review of TE Code of small and medium complexity.
  • May contribute to technical process and quality improvement to achieve high quality deliveries
  • Will be expected to Solve complex / abstract problems
  • The candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases in CRV environment.
  • The candidate will work in a project and team oriented environment with teams spread across multiple sites, worldwide.
  • May need to take the role of technical lead for a few of the components of the Test Environment and achieve high quality verification with a small team of verification engineers.
  • Must have BSEE in EE with 7+ years of relevant experience or MSEE with 6+ years of relevant experience in the following areas :

  • Verification of IP Cores or SoC Designs for Set Top Boxes, Mobile handsets, Smart Devices, etc.
  • Knowledge of one or more of protocols : DDR / Ethernet / USB / SDMMC / AMBA (AMBA2, AXI) / MIPI
  • Hands on experience with creating detailed design of certain components of Test Environment from Functional Specifications / Test Environment Specifications.
  • The TE must have used methodologies such as UVM / VMM / OVM.

  • Hands on experience with System Verilog / VERA / Specman coding and Simulation tools; Knowledge of C++ / OOPs Concepts
  • Experience with Perforce or similar revision control environment
  • Knowledge of Perl / Shell scripts.
  • Exposure to quality processes in the context of IP design and verification is an added advantage
  • Ability to work / Prior experience as a Technical Lead for a small team is a major plus.
  • In addition, the candidate will have good communication skills, will be a team player and will have good problem solving skills

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