Job Description :
Strong knowledge and experience in Scan Insertion, Compression, ATPG, Memory BIST and JTAG at IC level for mixed signal designs
Experience in using Mentor DfT tools, Synopsys DC and Tetramax and simulator tools.
Define DfT Strategy and Requirement Specification for the design
DfT verification for gate-level and timing simulations
Work cross sites with design team to define and implement DfT.
Hands on experience in solving DfT problems, simulation failures, ATPG coverage and DRC improvements.
Work with STA engineer to define timing constraints for DfT modes. Hands on experience on Primetime will be required.
Work with Layout engineer to see DFT logic is getting implemented without any issues.
Support Test engineer in silicon debug and pattern delivery for ATE.
Experience in RTL coding, shell / Perl scripting.
Knowledge of System Verilog Interfaces and Lint checks preferred.
Experienced in handling analog IP DfT simulations.
Be fluent with all common concepts of DfT and DfT tools.
Experience : 10 + Years
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.