Senior CAD Manager
AQUANTIA CORP
Bangalore
5h ago

The Opportunity

The successful candidate will have overall responsibility of setting the strategy and execution of CAD tools, flows and methodology for industry leading cutting edge SOC development on advanced process technologies(sub 10nm).

In addition, the candidate will oversee local work force of highly talented engineers .

Description

As a Senior CAD Manager you will be involved in driving all phases of Synthesis ,LEC and Place&Route tools,flows and methodologies which will be leveraged by multiple high performance SOCs from Netlist to delivery of our final GDSII.

Your responsibilities include managing engineers who

  • Develops CAD infrastructure to support scalable SAPR,DFT and Signoff flows.
  • Build block level and SOC level Tools,Flows and Methodologies for wider scale consumption
  • Support design community and build quality documentations around best-in-class flows.
  • Participate in establishing CAD and physical design methodologies for correct by construction designs
  • Work across the company in establishing best known practices for SOC methodology, execution and tracking.
  • Work with EDA vendors and process technologists to establish best in class tool selection for sub 10nm process technologies.
  • Key Qualifications

  • Organizational ability to lead and manage multiple areas of tool and methodology development and support various SoC projects concurrently.
  • Strategic focus to understand industry landscape of EDA tools and infrastructure in addition to building a scalable infrastructure globally for advanced process technologies.
  • 10+ years of Physical Design / CAD experience on high performance cpu and / or SOC designs
  • Knowledge about industry standards and practices in Physical Design, including Physically aware synthesis and Place & Route Experience in developing and implementing Power grid and Clock specifications
  • Working Knowledge of SOC architecture including RTL and pre-Silicon functional verification is a plus
  • Collaborate with logic design team for timing and electrical fixes using standard Physical Design & Synthesis tools
  • Proven Understanding of scripting languages such as Perl / Tcl and a Working knowledge of Extraction and STA methodology tools
  • Experience in DFT and ATPG flows is a plus
  • Highly refined organizational design, matrix management and collaborative skills
  • Advanced project management skills with ability to deliver flows and methodologies on time with quality for first time Silicon to production.
  • Education & Experience

    BS / MS / PHD EE,CE or CS

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