THE ROLE :
The Core design and verification team is responsible for development of High performance and Ultralow power x86 microprocessor core’.
The role provides a unique opportunity to work at the micro-architectural level of the next-gen Core, with exposure to designs that defines the next wave of client (laptops / ultra-books / think-clients) and custom designs.
The multi-billion gate complexity and high-frequency (GHz) design development gives the learning experience of the latest and greatest design and verification methodologies, using cutting edge advanced technology nodes.
THE PERSON :
Candidates should have solid track record of working on complex designs with hands on experience on architecting and developing test-bench, test-bench components, test-planning and execution of testplan, coverage development and closure.
Candidate should have working experience with global teams spread across different geography and time-zones.
KEY RESPONSIBILITIES :
ASIC design verification experience 8 to 12 years.
Verification of high performance x86-core ISA features
Architecting and development of testbench, test-bench components for high performance Cache, x86 ISA features, clock / reset / power features of processor.
Development of detailed test plans and driving the execution of test plan, including functional coverage.
Understanding the existing test bench setup and look for opportunities to improve the existing test bench.
Adhering to coding guideline practices, develop and implement code review process.
Collaborate with global design verification teams and drive effectively the execution of the verification plans.
Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion.
PREFERRED EXPERIENCE :
Strong understanding the design and verification life cycle.
Hands on verification experience with C / C++ / SystemVerilog testbench development.
Hands on experience with coverage planning, coding and coverage closure.
Experience with x86, ARM or any other industry standard microprocessor ISA.
Experience with Cache, Coherency and Data-Consistency verification.
Experience in clocking, reset, power-up sequences and power management verification.
Knowledge of microprocessor design-for-debug (DFD) logic will be a plus.
Understanding of low power design verification techniques is a plus.
ACADEMIC CREDENTIALS :
Master’s degree preferred with emphasis in Electrical / Electronics Engineering, Computer Engineering, or Computer Science with a focus on computer architecture