Design Engr Lead - Emulation / Verification
NXP Semiconductors
Noida
1d ago

NXP Semiconductors N.V. (NASDAQ : NXPI) enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better, and safer.

As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets.

Built on more than 60 years of combined experience and expertise, the company has over 29,000 employees in more than 30 countries and posted revenue of $8.88 billion in 2019.

Job Opportunity :

Seeking highly motivated, energetic, walk the talk’ attitude Tech Lead willing to take the challenge of delivering the first pass success of complex microcontroller based SoCs and IPs using the latest advanced verification languages and methodology.

The Verification Lead would be working with experienced and motivated team of Systems, Physical design, DFT, Mixed Signal and other local / remote teams to address the verification challenges in the context of the block, chip, and overall system, through the use of simulation, hardware modeling, formal verification and active participation in pre / post silicon validation.

Key Responsibilities :

  • Evaluate and deploy the evolving verification methodologies to handle increasingly complex SoC / IP designs within aggressive, market-driven schedules.
  • Ensure quality adherence during all stages of the project life cycle. Also carry out a thorough analysis of existing processes and recommend and implement the process improvements to ensure Zero Defect’ chips
  • Ability to think differently, encouraging and influencing technological innovations in the team
  • Ability to work well as part of a team both locally, and also with remote or multi-site teams
  • Driven and competitive when dealing with the outside, collaborative when dealing with the inside
  • Key Skills :

  • Self starter with 6-8 years of experience on SOC / Chip level / Cluster / IP verification on multimillion Gate and complex Design with multiple clocks and power domains with minimal supervision
  • Testbench and Testplan development to address Analog / Mixed signal and Testability aspects of the chip along with functional requirements
  • Understanding of the design issues in the RTL
  • Experience and working knowledge of HVLs (SV / C++ / SC / e / VERA), HDLs (Verilog / VHDL),PLI / DPI, simulators (IUS / Questa / VCS) is a MUST
  • Experience in microcontroller architecture, Cores ARM A / M series, Interconnect(NIC, FlexNoC), Cache, protocols like AHB / AMBA,AXI, ACE, OCP, Memory(Flash, SRAM,DDR3 / 4) and memory controllers
  • Experience in automotive protocols like LIN, CAN, Flex, Graphics / Multimedia / Networking protocols like PCIe, MIPI, H.
  • 264, Ethernet, USB, ITU T.656 would be an advantage

  • Exposure to formal verification methodology, assertions / SVA, functional coverage, gate level simulations, verification planner and regression management
  • Experience in Low power verification using CPF / UPF
  • Exposure to pre silicon validation / emulation (Palladium, Zebu) would be a big advantage
  • B.Tech / M.Tech (ECE or Electrical)

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