Principal Engineer ASIC DV
Our client is a world leader (Top4 Semicon Company in 2020) in innovative memory solutions that transform how the world uses information.
Location : Bangalore
This position is a permanent position with our client (US Based Semiconductor Product Company )
Principle Engineer ASIC DV
Verify the RTL code for the high speed SerDes IP and its related digital blocks along with compliance with the standard body protocols such as MIPI, PCIe etc.
Responsible for overall IP and sub-system verification from test plan creation, UVM development to signoff.
Ensure first pass product through multi-dimensional verification coverage including mixed mode verification.
Pair with Architects, Digital, SoC DV and FW engineers across the geographies for flawless execution and first-time silicon pass.
Leading, mentoring and coaching junior team members
Work closely with Digital and Analog designers
Equal opportunity position with excellent pay package!
Experience in design verification of complex high speed SERDES PHYs such as MIPI, PCIe etc Proven track record of building testplan, UVM environment and testbenches Experience with RTL debugging, score boarding and code coverage analysis Sound knowledge of Verilog and System Verilog languages Exposure to modeling and validating complex analog circuits in Verilog and Verilog-A Experience of complex mixed signal design verification using state of the art flows and tools The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams.
Team leadership experience, including planning and managing tasks is desirable M.S. / M.Tech, BS / BE (Electronics) Experience Required : 10+ Years
Contact : Uday Bhaskar
Mining the Knowledge Community"
Email id : muday bhaskar yahoo.com