Dft Sr Lead manager sr Engineer
Access Automation Private Limited
Bengaluru Bangalore
3d ago
source : IndianFresher

Candidate must have handled scan insertion, pattern generation amp; simulations timing sims , debug, handled different ATPG tools and flows, understand scan compression flows Should understand controllability and observability concepts, should understand why DFT coverage is important and how to improve coverage Ideal candidate should have done DFT architecture and planning for a full chip, by himself Usage of functional test patterns to improve test coverage, analog blocks test exposure not necessary .

  • Education : B e b tech,m e m tech ms
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