Develop Array / MBIST full chip test methodology and content for Intel's FPGA products Development activity includes(not limited to) on-chip DFT(Design For Test) definition, test vector generation / verification(simulation) and content bring up and optimization on silicon.
Collaborate with worldwide cross-functional teams including designers, software, manufacturing as you drive for test capability throughout entire product life cycle.
Drive test optimizations to reduce test cost, enhance product yield and quality, improve manufacturing efficiency and accelerate manufacturing stability.
Develop CMT / HDMT test module, conversion test pattern from STIL to pobj, doing test program validation on tester.
BS / MS in Electronics Engineering or equivalent, with industry experience in IC Design, IC Test, or equivalent field. Expert understanding of test methodology for ASIC, SOC and / or FPGAs.
Experience in test content development activities, running simulation and silicon bring-up MBIST test knowledge is preferable, with good understanding on memory BIST testing.
Verilog knowledge, ATE / tester knowledge with hands-on experience and DFT definition development experience is an added advantage.
Familiar with Yield improvement and Test Time reduction activities Strong digital circuit and VLSI fundamentals. Well versed in test industry trends and technology.
Self-motivated, passionate on problem solving and debugging issues with proven collaboration and leadership skills