ASIC Design Lead (CPU Subsystem)
3d ago

Job Overview : - Person will be working on ARM cortex-A series of cores as well as RISC-V cores and is responsible for Subsystem RTL Design - Person will be responsible for performing Digital Design Checks on the subsystem RTL like Clock Domain Crossing Checks, Low Power Checks, Lint Checks and basic Simulation.

  • Person will be handling communication with the various teams Verification / Implementation / SoC / Emulation / SW and ensuring timely & quality deliverables.
  • Minimum Qualifications : - Experience 6 to 13 Yrs in RTL Design - Should have B.E / B.Tech / M.E / degree from a reputed engineering college.
  • Should have good know-how of Verilog / System Verilog and able to Debug the design Failures. - Should have good understanding of Digital Design Flow (CDC, Low Power, HDL Simulation, Synthesis) & Tools - Preferred to have know-how of ARM Cortex-A series Cores like A53 / A73 / A55 ;
  • AMBA Busses - AXI, AHB, ATB, APB and Associated Peripheral / Debug components. - Knowledge of Version Control tools like Clearcase, scripting languages like perl / tcl will be an added advantage

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