Role : Physical Design Engineer
Experience : 2- 12 yrs
Job Description :
Chip level floorplanning, partitioning, timing budget generation, powerplanning, top PnR, CTS , block integration and ECO generation.
Block level implementation from netlist to GDS
Handling timing closure of high frequency blocks
Expertise in signoff closure Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level
Understanding constraints and fixing techniques
Understanding SI prevention , fixing methodology and implementation
Proficient in layout edit techniques
Proficient in Synopsys ICC,
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