R&D Engineer, Sr I
Synopsys
Bangalore, INDIA
3h ago

and Requirements

HAPS is Synopsys' industry leading FPGA-based prototyping system, providing state of the art hardware (FPGA based) and cutting edge software (ProtoCompiler) to deliver the best-in-class integrated prototyping solution.

ProtoCompiler software provides fast, automatic methods for conversion and partitioning of large ASIC designs onto HAPS multi-FPGA prototyping boards and includes powerful debugging features for verifying the designs.

See more details at https : / / www.synopsys.com / verification / prototyping.html

We are looking for an R&D engineer who is interested in developing complete (HW & SW) FPGA prototyping solutions. Someone who is excited to develop complete systems by doing both digital design and SW development. The person is expected to -

  • Experience in designing for Xilinx and Altera FPGA’s.
  • Relevant exposure to tools like Xilinx ISE, Xilinx PlanAhead, Altera Quartus II.
  • Extensive involvement in all stages of Project development life cycle including Requirements, Development, Implementation, Test Case development.
  • Work with CAE team in test planning, execution, and customer support.
  • Experience in developing large complex EDA software.
  • Experience in digital debug / verification / emulation / prototyping.
  • Experience in RTL development for interfaces like USB, PCIe, DDR, AXI.
  • Experience in full design flow including verification and lab bring up.
  • Exposure to embedded system development.
  • Maintain and support existing product and features.
  • Investigate new ways to solve customer’s current and future needs, constantly learning on the job.
  • Prior knowledge and experience of CAD tool development are required
  • Determines and develops approach to solutions.
  • Work is independent and collaborative in nature.
  • Guides more junior peers with aspects of their job. Frequently networks with senior internal and external personnel in own area of expertise.
  • Requirements :

  • MS / PhD in CS / EE from a reputed institute with 10+ years of relevant experience.
  • Knowledge of RTL development (Verilog or System Verilog).
  • Excellent C / C++ coding, and a strong background in data structures and algorithms
  • Complex Problem solving and debugging skills.
  • Experience with scripting (Tcl, Python, Perl etc).
  • Good understanding of System & CPU architecture (DMA, Interrupts etc).
  • Employee

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