FCT Engineer

INVECAS

Hyderabad, Telangana, IN

6h ago

Hands on experience with Timing Analysis of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm)

Lead STA activities on SoC designs with expertise in Constraints creation, CDC checks and Pre / Post Layout Timing closure

Expertise in Timing constraints creation for FE / BE, time budgeting, constraints coverage analysis, Timing closure techniques in MMMC environment

Work closely with CAD teams and involve in timing methodology development and improvement

Own SoC timing activities while managing a team of 5-10 engineers

Desired Skills and Experience :

B. Tech. / M. Tech. with 5-10 years of experience in STA

The candidate should be able to work with and lead a team of engineers working on Timing closure for SOC design

Should have handled STA for at least 2-3 SoC designs on lower technology nodes

Excellent understanding of timing closure techniques & SI analysis / fixes in lower technology nodes in high-speed designs with DDR, Serdes, USB interfaces

Experienced in industry standard tools viz. Synopsys PT, Cadence Tempus

Knowledge in TCL, Perl scripting is a must

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