FPGA group in Synopsys delivers a number of products such as Synplify Pro, Synplify Premier, ProtoCompiler, Protosynthesis and Identify.
These products are widely used in the industry for implementation of FPGA designs, prototyping and debugging of ASICs using FPGAs.
Logic synthesis software, which is part of Synplify Pro and Synplify Premier products, is the industry standards for producing high-performance, cost-effective FPGA designs.
Its unique Behavior Extracting Synthesis Technology® (BEST™) performs optimization at a high level first, before synthesizing the RTL code into specific FPGA logic.
This approach allows for best optimization across the FPGA, provides fast runtimes and support for very large designs.
Looking for a Senior R&D engineer with 11+ years of experience in EDA tool development or software development experience for our technology mapper R&D team in Bangalore with the given background / skill sets.
Roles and responsibility :
A person in the position would be responsible for designing, developing, troubleshooting, debugging and maintaining large and efficient software systems for technology mapping, logic and timing optimization steps of the FPGA logic synthesis software.
The person is expected to
Write requirement and functional specifications, design and implement efficient data structures and algorithms in C / C++.
Incorporate advanced software engineering tools and processes related to documentation and coding practices, memory and runtime profiling, coverage, unit testing in the development process.
Work with Application Engineering team in test planning, execution and customer support.
Maintain and support existing product and features.
Expected background and skill :
The person is expected to have :
B.Tech / M. Tech / PhD in CS / EE from a reputed institute.
11+ years of experience in designing, developing and maintaining large EDA software.
Solid background in digital logic design.
Expertise in data structures, graph algorithms and C / C++ programming on Windows / Unix.
Good familiarity with Verilog / VHDL RTL level designs, timing constrains, static timing analysis.
Working knowledge of FPGA design tools and flows.
Experience with tools such as Valgrind, purify, coverity etc.