Requirements : Analog and Mix signal block connectivity verification at RTL and gate level. Integrate analog models with RTL and GATE simulation environment.
Define test strategy for Analog blocks - create test plan , define test concurrencies. Responsible for test pattern generation based on timing simulation , release for ATE and Post silicon debug.
Support silicon characterization and bench level testing by working with design , verification , bench and test teams. Responsible for system level verification for complex SOC which has digital , analog and RF components.
post - silicon debug of analog blocks is desirable Expertise in verifying complex designs from system as well as block level , through design flow.
Experience in VERA , MODELSIM , Debussy , C Knowledge on Perl or any other scripting language Exposure to post silicon debug ATE testing / Bench / application testing Ability to work in an international team , dynamic environment with good communication skills Ability to learn and adapt to new tools , methodologies.
Ability to do multi - tasking work on several high priority designs in parallel. Experience : 4 to 6 years Educational Qualification BE / BTech or ME / MTec,