R&D Engineer, Staff
Synopsys, Inc
INDIA - Bangalore
6d ago

Job Description and Requirements

Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars.

Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything where devices are getting smarter, everything’s connected, and everything must be secure.

Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them.

Synopsys is at the forefront of Smart, Secure Everything with the world’s most advanced tools for silicon chip design, verification, IP integration, and application security testing.

Our technology helps customers innovate from Silicon to Software, so they can deliver Smart, Secure Everything.

Founded in 1986, $2.7B+ Synopsys employs 12,000+ headquartered in Mountain View, California, located globally in over 25 countries with 113+ offices throughout North America, Europe, Japan, Asia, and India.

Synopsys is committed to fostering an environment that treats people with respect, honesty and professionalism. We’re also committed to partnering with the communities in which we work.

Every year, Synopsys reaches out to local communities with resources and employee leadership to support education, science programs and a variety of other activities.

Come and be part of a collaborative team environment that innovates and develops the latest IP solutions that enable the way the world designs. Join US!

Digital ASIC Design / Verification Engineer

IP Subsystem Solution Team at Synopsys is looking for a Digital ASIC Design / Verification Engineer. In this role you will be responsible for RTL design, developing test benches and verifying integrated IP Subsystems for our customers.

Must understand one or more of the following protocols USB, PCIE, SATA, DDR, Ethernet, HDMI, DP and MIPI. Strong experience in ASIC verification using UVM is required.

Able to design test benches to verify RTL, debug simulation failures, write verification plans, and converge on coverage goals.

Also in this position he / she should be able to do Architecture, Micro-architecture, RTL design and proficient in documentation, datasheets and technical presentations.

Requirements :

  • BS in EE / CS with 10+ years of experience. MS is preferred.
  • Knowledge of System Verilog and UVM to develop test benches for RTL simulations
  • Experience in RTL development using Verilog / System Verilog.
  • Experienced in high speed memory interfaces (DDRx)
  • Experience in creating test plan and constrained random tests to meet coverage
  • Experience in creating code coverage and functional coverage plans and reports
  • Knowledge of UPF based low power design verification is a plus
  • Ability to work independently and good interpersonal skills
  • Apply
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