Verification-Engineer
Qualcomm
Bangalore
6d ago

Company :

Qualcomm India Private Limited

Job Area :

Engineering Group, Engineering Group >

Qualcomm Overview :

Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives.

But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products.

This is the Invention Age - and this is where you come in.

General Summary

You will be responsible for SOC level verification of NOCs(Network on a chip) blocks and Interface buses. You will be contributing / leading the verification effort on cutting edge technology for complex Snapdragon series of SOCs You will be responsible for verification plan definition, DV environment development in SV / UVM, SV / C based test case development, Design verification at RTL level, DV Coverage analysis, Coverage improvement at block and SOC level, System scenario and use case verification, Power and Performance analysis for your blocks in SOC, Gate level verification, Functional test vector development and Silicon bring up debug support.

5-8 years’ experience in Design verification in product company on real projects.

Knowledge about ARM architecture, AMBA protocols & working knowledge of VIPs.

Expertise in verifying complex designs from system as well as block level, through design flow.

Experience in building SV-UVM test environment / Assertion based verification.

Experience in coverage closure and test case improve to improve coverage

Experience in SYSTEM VERILOG, UVM, VERA , MODELSIM / VCS / SILOTI

Knowledge on Perl or any other scripting language

Understanding of RTL design / verification concept

Excellent written and oral communications skills.

Minimum Qualifications : 2-5 years’ experience in Design verification in product company on real projects. Knowledge about ARM architecture.

Experience in building SV-UVM test environment / Assertion based verification. Experience in coverage closure and test case improve to improve coverage Experience in SYSTEM VERILOG, UVM, VERA , MODELSIM / VCS / SILOTI Knowledge on Perl or any other scripting language Understanding of RTL design / verification concept Prior knowledge on security blocks, JTAG verification is an added advantage Excellent written and oral communications skills.

B Tech / M Tech in ECE / CSE from reputed institutes.

Minimum Qualifications

Education :

Bachelors - Computer Science

Work Experiences : Certifications :

Certifications : Skills :

Skills :

RTL Coding, SoC Verification, SystemVerilog, Universal Verification Methodology (UVM), VHDL

Preferred Qualifications

Education : Work Experiences :

Work Experiences :

4+ years Hardware Engineering experience or related work experience.

Certifications : Skills :

Skills :

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