Job Description :
Strong knowledge in SOC design methodologies.
Sound knowledge of SOC integration, RTL design with Verilog / system Verilog and front-end design tools & flows.
Good communication skills to work in a cross functional global IP teams and SOC cross functional teams ( Verification, PD, DFT).
Must be able to participate& contribute effectively in global meetings
The design engineer should be aware of SOC architecture and knowledge of SOC system IPs ( memory controller, system interconnect, power management etc.)
Sound knowledge in standard RTL coding guide lines
Basic synthesis knowledge & timing required
Must have strong knowledge of AMBA AHB / AXI protocol
Working knowledge on code coverage, functional coverage, Lint, CDC etc
Low power design
Good technical leadership skills.
Mentoring juniors and enhancing their skill set
Educational Qualifications : B.E / B.Tech or M.E / M.Tech degree in ECE / Electrical Engineering with Digital Systems / VLSI as major