Principal RTL Design Engineer (Serdes)
Cadence Design Systems
Bengaluru, Karnataka, India
1d ago
source : Linkedin
  • Good experience in microarchitecture, design, synthesize for a complex DSP based SerDes IP in various technology nodes.
  • Proficient in RTL coding, DSP-based datapath designs, complex FIFO, calibration and Soft IP to Hard IP I / F designs etc..
  • Strong knowledge of complete design flows and rigorous checks before delivery to other teams or customers ex- LINT, SDC, CDC, DFT, Low power, and trial PnR
  • Desired Protocols knowledge can be any of the Industry Std Serdes’es 1G-100G Ethernet, USB, PCie1-6, MIPI(DPHY), HDMI / Display
  • Work closely with Analog design teams to co-develop algorithms, feedback design loops as well as high speed critical digital circuits at lower geometry nodes of 7nm and below
  • Working on GLS closure with SV DV, PD, and Modeling skills to ensure critical performance
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